The present disclosure relates to a processor. More particularly, the disclosure relates to a processor that presupposes the use of a VLIW (Very Long Instruction Word) type parallel execution portion or the like.
Sequential execution processors such as RISC (Reduced Instruction Set Computer) processors are suited for general-purpose control processes. Parallel execution processors such as VLIW processors, on the other hand, are good at performing simple and numerous parallel execution processes for specific purposes. Usually, these two types of processors each possess an independent instruction cache or RAM (Random Access Memory) and operate independently (issuing and executing instructions). That is, RISC-side processes and VLIW processor processes do not mix; they can exchange information solely on a shared memory at a higher layer. It is difficult to merge these two kinds of processes in minute increments.
In the past, there were proposed processors that use subroutine instruction codes of RISC processor instructions to operate a VLIW control unit (e.g., see Japanese Patent Laid-Open No. 2002-032218 (FIG. 1)). The proposed technique involves using subroutine instruction codes to designate program numbers causing the VLIW control unit to start program execution. This allows the VLIW control unit to carry out parallel execution.